1. Field of the Invention
The present invention relates to a data communication system, and more particularly, to a system and method for communicating data over communications channels.
2. Description of the Related Art
FIG. 1 is a diagram illustrating a conventional communication system. Referring to FIG. 1, the communication system 5 includes a transmitter 10, a receiver 20, and communication channels CH1 through CH4. Data DO00 through DO03 of the transmitter 10 are transmitted to the receiver 20 through the communication channels CH1 through CH4.
FIG. 2 is a schematic diagram illustrating an environment in which simultaneous switching noise (SSN) occurs during data communication between two semiconductor memory devices. Referring to FIG. 2, a first semiconductor memory device 30 (memory device 1) operates as a transmitter, and a second semiconductor memory device 40 (memory device 2) operates as a receiver. The first semiconductor memory device 30 includes output drivers 31 through 34 operating at a high power supply voltage VDDQ and a low power supply voltage VSSQ. The second semiconductor memory device 40 includes input drivers 41 through 44 operating at the high power supply voltage VDDQ and the low power supply voltage VSSQ.
FIG. 3 is a schematic diagram illustrating an environment in which inter-symbol interference (ISI) occurs during the data communication between the two semiconductor memory devices. In FIG. 3, the communication channel CH2 of the communication channels CH1 through CH4 in FIG. 2 is illustrated, and data D1 passes through the communication channel CH2. Parasitic capacitance CCH exists between the ground and the communication channel CH2 disposed outside of a semiconductor chip. The parasitic capacitances CCH also exist between the ground and the communication channels CH1, CH3 and CH4.
FIG. 4 is a diagram illustrating data affected by ISI and SSN during transmission through four communication channels, and the data include bits highly susceptible to errors. Referring to FIGS. 2 and 4, each of the four data D0-D3 includes nine bits, which are sequentially transmitted through the communication channels CH1 through CH4. The data D0 is transmitted through the communication channel CH1, the data D1 is transmitted through the communication channel CH2, the data D2 is transmitted through the communication channel CH3, and the data D3 is transmitted through the communication channel DH4, respectively. A reference numeral 51 corresponds to a data bit susceptible to errors affected by ISI. A reference numeral 52 corresponds to data bits susceptible to errors affected by SSN.
Referring to FIGS. 3 and 4, a state of the data D1 changes from a second bit “0” to a third bit “1”, and then from the third bit “1” to a fourth bit “0” as indicated by the reference numeral 51. A voltage of the third bit “1” is not high enough to be recognized as a logic high when the state of the data D1 changes from 0 to 1 to 0 because the communication channels have the parasitic capacitances, as indicated in FIG. 3. Also, a voltage of “0” is not low enough to be recognized as a logic low when the state of the data D1 changes from 1 to 0 to 1. This phenomenon is referred to as ISI.
Referring to FIGS. 2 and 4, a state of the data D0 changes from “1” to “0” while states of the data D1 through D3 change from “0” to “1”, as indicated by the reference numeral 52. The output driver 31 connected to the communication channel CH1 may output “1” instead of “0” in a first row shown by the reference number 52, when the data D0 transmitted through the communication channel CH1 changes from “1” to “0” and the states of the data D1 through D3 transmitted through the communication channels CH2 through CH4 change from “0” to “1” in the second through fourth rows, as indicated by the reference numeral 52. This phenomenon is referred to as SSN.
Further Bit Error Rate (BER) during transmission through communication channels between semiconductor chips increases as a communication between the semiconductor chips becomes faster. Accordingly, there exists a probability of error occurrence caused by ISI and SSN.